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24c02/04/08/16 1 24c02 / 24c04 / 24c08 / 24C16 2k bits (256 x 8) / 4k bits (512 x 8) / 8k bits (1024 x 8) / 16k bits (2048 x 8) t w o-wire serial eeprom features tw o-w i re serial interface v cc = 1.8v to 5.5v bi-directional data transfer protocol internally organized 24c02, 256 x 8 (2k bits) 24c04, 512 x 8 (4k bits) 24c08, 1024 x 8 (8k bits) 24C16, 2048 x 8 (16k bits) 1 mhz (5v), 400 khz (1.8v, 2.5v, 2.7v) compatibility 8-by te page (2k), 16-by te page (4k, 8k, 16k) write modes self-timed write cy cle (5 ms max) 1 million write cy cles guaranteed data retention > 100 y ears operating temperature: -40 to +85 8-lead pdip, 8-lead sop and 8-lead tssop packages description 24c02/24c04/24c08/24C16 provides 2048/4 096/8192/16384 bits of serial electrically erasa b le and p r ogramma bl e read- onl y m e m o r y (eep ro m) organ ize d as 256/5 12/1 0 2 4 /204 8 w o r d s of 8 bits eac h. t h e devic e is o p timize d for u s e in m a n y in dustria l an d c o mmercia l ap plicati ons w h e r e lo w - p o w e r and lo w - volta ge o perati ons are ess enti a l. t he bl24c 02/bl 2 4 c0 4/bl2 4 c0 8/bl24 c1 6 is avail a b l e i n sp ace-sav i ng 8-le ad pdip, 8-l e a d so p, and 8- l ead t ssop packages and is accesse d via a tw o-w i re serial interface. pin descriptions tiger electronic co.,ltd
24c02/04/08/16 2 block diagram
24c02/04/08/16 3 device/page addresses (a2, a1 and a0): the a2, a1 and a0 pins are device address inputs that are hard wired for the 24c02. eight 2k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). the 24c04 uses the a2 and a1 inputs for hard wire addressing and a total of four 4k devices may be addressed on a single bus system. the a0 pin is a no connect and can be connected to ground. the 24c08 only uses the a2 input for hardwire addressing and a total of two 8k devices may be addressed on a single bus system. the a0 and a1 pins are no connects and can be connected to ground. the 24C16 does not use the device address pins, which limits the number of devices on a single bus to one. the a0, a1 and a2 pins are no connects and can be connected to ground. serial data (sda): the sda pin is bi-directional for serial data transfer. this pin is open-drain driven and may be wire-ored with any number of ot her open-drain or open- collector devices. serial clock (scl): the scl input is used to positive edg e clock data into each eeprom device and negative edge clock data out of each device. write protect (wp): the 24c02/24c04/24c08/24c 16 has a write protect pin that provides hardware data protection. the write protect pin allows nor mal read/write operations when connected to ground (gnd). when the wr ite protect pin is connected to vcc, the write pr otection feature is enabled and operates as shown in the following table 2. part of the array protected wp pin status: 24c02 24c04 24c08 24C16 at v cc full (2k) array full (4k) array full (8k) array full (16k) array at gnd normal read/write operations memory organization 24c02, 2k serial eeprom: internally organized with 32 pages of 8 bytes each, the 2k requires an 8-bit data word address for random word addressing. 24c04, 4k serial eeprom: internally organized with 32 pages of 16 bytes each, the 4k requires a 9-bit data word address for random word addressing. 24c08, 8k serial eeprom: internally organized with 64 pages of 16 bytes each, the 8k requires a 10-bit data word address for random word addressing. 24C16, 16k serial eeprom: internally organized with 128 pages of 16 bytes each, the 16k
24c02/04/08/16 4 requires an 11-bit data word address for random word addressing. device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see to figure 1 on page 4). data changes during scl high periods will indicate a start or stop condition as defined below. start condition : a high-to-low transition of sda with scl high is a start condition which must precede any other command (see to figure 2 on page 4). stop condition : a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 2 on page 4). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a "0" to acknowle dge that it has received each word. this happens during the ninth clock cycle. standby mode: the k24c02/k24c04/k24c08/k24C16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations memory reset : after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. clock up to 9 cycles. 2. look for sda high in each cycle while scl is high. 3. create a start condition.
24c02/04/08/16 5 device addressing t he 2k, 4k, 8 k and 16k eeprom devices all requir e an 8-bit device a ddress w o r d follo w i n g a start condition to enable the chip for a read or w r ite operation (see to f i gure 4 on page 7). t he device a d d ress w o r d co n s ists of a man d a tor y "1", " 0 " s equ enc e for th e first four mos t signific ant bit s as show n. t h is is common to all the serial eeprom devices. t he nex t 3 bits are the a2, a1 and a0 device addr ess bits for the 2k eeprom. t hese 3 bits must compare to their corresponding hardw ired input pins. t he 4k eepr om onl y us es the a2 and a1 device ad dr es s bits w i th the third bit bei ng a memor y pag e addr ess bit. t he t w o d e vice a ddress bits mu st compare to t heir c o rresp on din g har d w ir ed inp u t pins. t h e
24c02/04/08/16 6 a0 pin is no connect. the 8k eeprom only uses the a2 device address bit with the next 2 bits being for memory page addressing. the a2 bit must compare to its corresponding hard-wired input pin. the a1 and a0 pins are no connect. the 16k does not use any device address bits but instead the 3 bits are used for memory page addressing. these page addressing bits on the 4k, 8k and 16k devices should be considered the most significant bits of the data word address whic h follows. the a0, a1 and a2 pins are no connect. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a "0". if a compare is not made, the chip will return to a standby state. write operations byte write: a write operation requires an 8-bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a "0" and then clock in the first 8-bit data word. following receipt of the 8-bit data word, t he eeprom will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an intern ally timed write cycle, twr, to the nonvolatile memory. all inputs are disa bled during this write cycl e and the eeprom will not respond until the write is complete (see figure 5 on page 7). page write: the 2k eeprom is capable of an 8-byte page write, and the 4k, 8k and 16k devices are capable of 16-byte page writes. a page write is initiated the same as a byte write, but the microcont roller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2k) or fifteen (4k, 8k, 16k) more data words. the eeprom will respond with a "0" after each data word received. the microcont roller must terminate the page write sequence with a stop condition (see figure 6 on page 7). the data word address lower three (2k) or four (4k, 8k, 16k) bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, inter nally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than eight (2k) or sixteen (4k, 8k, 16k) data words are transmitted to the eeprom, the data word address will "roll over" and previous data
24c02/04/08/16 7 will be overwritten. acknowledge polling: once the internally timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bi t is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a "0", allowing the read or write sequence to continue. read operations read operations are initiated the same way as write operations with the exce ption that the read/write select bit in the device address word is set to "1". there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. t he address "roll over" during read is from the last byte of the last memory page to the first byte of t he first page. the address "roll over" during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input "0" but does generate a follo wing stop condition (see figure 7 on page 8). read operations random read: a random read requires a "dummy" byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condit ion. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a "0" but does generate a follo wing stop condition (see figure 8 on page 8). sequential read: sequential reads are initiated by eit her a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment t he data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a "0 " but does generate a following stop condition (see figure 9 on page 8).
24c02/04/08/16 8
24c02/04/08/16 9
24c02/04/08/16 10 electrical characteristics
24c02/04/08/16 11 ac electrical characteristics bus t i ming w r ite cycle t i ming
24c02/04/08/16 12 package information 8-lead pdip outline dimensions millimeter symbol m i n n o m m a x a 3 . 6 0 3 . 8 0 4 . 0 0 a 2 3 . 1 0 3 . 3 0 3 . 5 0 b 0 . 4 4 - 0 . 5 3 b 1 1 . 5 2 b s c c 0 . 2 5 - 0 . 3 1 c 1 0 . 2 4 0 . 2 5 0 . 2 6 d 9 . 0 5 9 . 2 5 9 . 4 5 e 1 6 . 1 5 6 . 3 5 6 . 5 5 e 2 . 5 4 b s c ea 7 . 6 2 b s c l 3 . 0 0 - -
24c02/04/08/16 13 8-lead sop outline dimensions millimeter symbol m i n n o m m a x a - - 1 . 7 7 a 1 0 . 0 8 0 . 1 8 0 . 2 8 b 0 . 4 4 - 0 . 5 3 c 0 . 2 1 - 0 . 2 6 d 4 . 7 0 4 . 9 0 5 . 1 0 e 5 . 8 0 6 . 0 0 6 . 2 0 e 1 3 . 7 0 3 . 9 0 4 . 1 0 e 1 . 2 7 b s c 0 - 8
24c02/04/08/16 14 8-lead tssop outline dimensions millimeter symbol m i n n o m m a x a - - 1 . 2 0 a 1 0 . 0 5 - 0 . 1 5 a 2 0 . 9 0 1 . 0 0 1 . 0 5 a 3 0 . 3 4 0 . 4 4 0 . 5 4 b 0 . 2 0 - 0 . 2 8 b 1 0 . 2 0 0 . 2 2 0 . 2 4 c 0 . 1 0 - 0 . 1 9 c 1 0 . 1 0 0 . 1 3 0 . 1 5 d 2 . 8 3 2 . 9 3 3 . 0 3
24c02/04/08/16 15 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e 0.65bsc l 0.45 0.60 0.75 l1 1.00ref l2 0.25bsc r 0.09 - - r1 0.09 - - s 0.20 - - 1 0 - 8 2 10 12 14 3 10 12 14

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